Logic state catching circuits
US7564266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jul 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.