Detecting excess current leakage of a CMOS device
US7564274B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system (10,90), apparatus (12,30,40,50,60,70) and method (100) is disclosed for detecting excess current leakage between drain/source of a metal oxide semiconductor (MOS) transistor (36,46) within a complementary MOS (CMOS) environment. A load control (32,42) is arranged as a compliment to the MOS transistor. A comparator (34,44) is electrically connected to the load control and the MOS transistor, and produces an output signal representative of the detection of a current leakage exceeding a threshold. In response to the received output signal indicating an excess current leakage, system voltage/frequency may be adjusted to prevent damage to the CMOS environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.