Bistable flip-flop having retention circuit for storing state in inactive mode
US7564282B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for storing the state of the device in the active mode, and retention means for storing the state of the device in the inactive mode. The device includes a continuously-powered bistable structure that integrates the retention means and part of the storage means. The bistable structure includes a single isolation switch connected to the inverter chain and controlled by a standby logic signal that is representative of the active or inactive mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.