High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital converter and related methods
US7564397B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 10, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.