Memory data transfer
US7564737B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jan 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.