System and method for reducing temperature variation during burn in
US7565259B2 · kind B2 · utility
64Cited by
37References
15Claims
0Family size
Inventors
Key dates
| Filing date | Jul 24, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jul 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2879
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.