Method of fabricating orientation-controlled single-crystalline wire and method of fabricating transistor having the same
US7566364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2006 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Aug 5, 2027 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC30B29/60
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Provided may be a method of fabricating nanowires and a method of fabricating a transistor having the same. The method may include: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed in the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface; supplying gaseous crystal growth materials through the second apertures; and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer. The nanowires may be made of crystalline materials, e.g., Si or SiGe, and may be formed parallel to the substrate. Higher quality nanowires, whose orientation may be controlled, may be formed. A higher quality transistor may be formed on the substrate by applying a method of fabricating the nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.