Method for the production of transistor structures with LDD
US7566624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2004 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/608
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a transistor structure with a lightly doped drain (LDD) includes structuring a gate electrode on a gate dielectric. The method also includes etching the semiconductor body or substrate to form sloping sidewails on regions adjacent to the gate electrode, and anisotropically back-etching the spacer layer to form spacers. The gate electrode is used as a mask to implant dopant to form a source region, a drain region, and regions of lower dopant concentration. Implanting dopant is performed at a first angle relative to the upper surface of the semiconductor body or substrate to form the source and drain regions, and at a second angle relative to the upper surface of the semiconductor body or substrate, and through the spacers, to form the regions of lower dopant concentration. The first angle is greater than the second angle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.