Method to reduce seedlayer topography in BICMOS process

US7566919B2 · kind B2 · utility

Assignee

• NXP B.V. · NL

Inventors

• Johannes Josephus Theodorus Marinus Donkers · Valkenswaard, NL
• Petrus Hubertus Cornelis Magnee · Malden, NL
• Eddy Kunnen · Kessel-Lo, BE
• Francois Neuilly · Colomby-sur-Thaon, FR

Key dates

• Filing date: Dec 9, 2004
• Grant date: Jul 28, 2009
• Expiry date: Aug 1, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).