Doped polysilicon via connecting polysilicon layers
US7566974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | May 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.