Tanmay Kumar
88Patents
16h-index
67Co-inventors
87Inventor score
Filing activity: Apr 26, 2000 → Jan 22, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7915164B2 | Method for forming doped polysilicon via connecting polysilicon layers | Electricity | 243 | Active |
| US7566974B2 | Doped polysilicon via connecting polysilicon layers | Electricity | 181 | Expired |
| US7875871B2 | Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride | Electricity | 109 | Active |
| US8227787B2 | Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride | Electricity | 101 | Active |
| US7830698B2 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same | Physics | 66 | Active |
| US8658476B1 | Low temperature P+ polycrystalline silicon material for non-volatile memory device | Electricity | 63 | Active |
| US7660181B2 | Method of making non-volatile memory cell with embedded antifuse | Electricity | 48 | Active |
| US7054219B1 | Transistor layout configuration for tight-pitched memory array lines | Electricity | 47 | Expired |
| US6306718A | Method of making polysilicon resistor having adjustable temperature coefficients | Electricity | 41 | Expired |
| US7812404B2 | Nonvolatile memory cell comprising a diode and a resistance-switching material | Electricity | 40 | Expired |
| US8946673B1 | Resistive switching device structure with improved data retention for non-volatile memory device and method | Electricity | 25 | Active |
| US7495947B2 | Reverse bias trim operations in non-volatile memory | Physics | 18 | Active |
| US7719874B2 | Systems for controlled pulse operations in non-volatile memory | Physics | 17 | Active |
| US7800933B2 | Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance | Physics | 17 | Active |
| US9806256B1 | Resistive memory device having sidewall spacer electrode and method of making thereof | Physics | 16 | Active |
| US9805794B1 | Enhanced erasing of two-terminal memory | Physics | 16 | Active |
| US8062918B2 | Surface treatment to improve resistive-switching characteristics | Electricity | 14 | Active |
| US7897453B2 | Dual insulating layer diode with asymmetric interface state and method of fabrication | Electricity | 13 | Active |
| US8971088B1 | Multi-level cell operation using zinc oxide switching material in non-volatile memory device | Physics | 13 | Active |
| US7492630B2 | Systems for reverse bias trim operations in non-volatile memory | Physics | 12 | Active |
| US8674724B2 | Field programmable gate array utilizing two-terminal non-volatile memory | Electricity | 12 | Active |
| US8754671B2 | Field programmable gate array utilizing two-terminal non-volatile memory | Electricity | 11 | Active |
| US7800934B2 | Programming methods to increase window for reverse write 3D cell | Physics | 11 | Active |
| US7944728B2 | Programming a memory cell with a diode in series by applying reverse bias | Physics | 10 | Active |
| US8659929B2 | Amorphous silicon RRAM with non-linear device and operation | Physics | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.