Nonvolatile memory array architecture
US7567457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.