Memory block testing
US7567472B2 · kind B2 · utility
21Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Apr 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.