Bipolar transistors with low parasitic losses

US7569872B1 · kind B1 · utility

Assignee

• HRL Laboratories, LLC · US

Inventors

• Rajesh D. Rajavel · Oak Park, US
• David H. Chow · Newbury Park, US
• Tahir Hussain · Calabasas, US
• Yakov Royter · Santa Monica, US

Key dates

• Filing date: Dec 20, 2005
• Grant date: Aug 4, 2009
• Expiry date: Mar 16, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85

Abstract

Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.