Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
US7569873B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jan 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.