Semiconductor device with close stress liner film and method of manufacturing the same
US7569888B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Mar 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure are generally directed to FETs with stress liners that are closer than typical stressed FETs, as well as methods for manufacturing the same. FETE channel sidewall spacers may be removed, or substantially reduced in width, prior to forming the stress liners. This may be performed without destroying the underlying thin oxide layer. The sidewall spacers may be removed substantially reduced either prior to or after silicide formation. Where the sidewall spacers are removed prior to silicide formation, a relatively thin oxide layer on opposing sides of the channel may be used as a mask when forming the silicide. In addition, devices having both an NFET with a closer-than-typical tensile liner and a PFET with a closer-than-typical compressive liner, as well as methods for manufacturing the same, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.