Gaku Sudo
34Patents
6h-index
24Co-inventors
65Inventor score
Filing activity: Aug 10, 2005 → May 20, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8835268B2 | Method for manufacturing semiconductor device | Electricity | 28 | Active |
| US7585720B2 | Dual stress liner device and method | Electricity | 25 | Active |
| US8592890B2 | Semiconductor memory device and method for manufacturing same | Electricity | 19 | Active |
| US8658504B2 | Method for manufacturing semiconductor device | Electricity | 10 | Active |
| US8866206B2 | Integrated circuit device and method for manufacturing same | Electricity | 6 | Active |
| US9142537B2 | Integrated circuit device and method for manufacturing same | Electricity | 6 | Active |
| US7727834B2 | Contact configuration and method in dual-stress liner semiconductor device | Electricity | 5 | Active |
| US9997526B2 | Semiconductor device and method for manufacturing same | Electricity | 5 | Active |
| US7402885B2 | LOCOS on SOI and HOT semiconductor device and method for manufacturing | Electricity | 4 | Active |
| US7569888B2 | Semiconductor device with close stress liner film and method of manufacturing the same | Electricity | 4 | Active |
| US8785325B2 | Method of manufacturing semiconductor device | Electricity | 3 | Active |
| US8154050B2 | Semiconductor device with semiconductor epitaxial layers buried in source/drain regions, and fabrication method of the same | Electricity | 3 | Active |
| US8659159B2 | Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same | Electricity | 3 | Active |
| US8129790B2 | HOT process STI in SRAM device and method of manufacturing | Electricity | 3 | Active |
| US9178064B2 | Method for manufacturing fin semiconductor device using dual masking layers | Electricity | 3 | Active |
| US9831270B2 | Nonvolatile semiconductor memory device and method for manufacturing the same | Electricity | 2 | Active |
| US7592653B2 | Stress relaxation for top of transistor gate | Electricity | 2 | Active |
| US10985209B2 | Nonvolatile storage device | Electricity | 2 | Active |
| US8004035B2 | Dual stress liner device and method | Electricity | 2 | Active |
| US10283647B2 | Semiconductor device | Physics | 2 | Active |
| US9117888B2 | Integrated circuit device and method for manufacturing same | Electricity | 1 | Active |
| US10090320B2 | Semiconductor device and method for manufacturing the same | Electricity | 1 | Active |
| US8790979B2 | Semiconductor device and method for manufacturing same | Electricity | 1 | Active |
| US8614138B2 | Manufacturing method of semiconductor device | Electricity | 1 | Active |
| US9384829B2 | Memory device | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.