Semiconductor memory device having a three-dimensional cell array structure
US7570511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Aug 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.