Circuit and method for generating data output control signal for semiconductor integrated circuit
US7570542B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jul 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.