Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7571284B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Dec 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is used to store load data returned by a memory unit in response to a request issued by a processing module, such as a stream processing unit, in a processing core. As requests are issued, a destination queue buffer ID tag is transmitted as part of the request. When the request is returned, that destination number is reflected back and is used to control which queue within the circular queue will be used to store the retuned load data. Separate pointers are used to indicate the order of the queues to be read and the order of the queues to be written. The method and apparatus implemented by the present invention allows out-of-order data to be processed efficiently, thereby improving the performance of a fine grain multithreaded, multi-core processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.