Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors
US7571301B2 · kind B2 · utility
12Cited by
5References
27Claims
0Family size
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Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jul 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.