Xinmin Tian
37Patents
9h-index
98Co-inventors
78Inventor score
Filing activity: Feb 19, 2003 → Jul 12, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7941791B2 | Programming environment for heterogeneous processor resource integration | Physics | 21 | Active |
| US8037465B2 | Thread-data affinity optimization using compiler | Physics | 21 | Active |
| US7398521B2 | Methods and apparatuses for thread management of multi-threading | Physics | 14 | Expired |
| US7657880B2 | Safe store for speculative helper threads | Physics | 13 | Expired |
| US7571301B2 | Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors | Physics | 12 | Active |
| US8612949B2 | Methods and apparatuses for compiler-creating helper threads for multi-threading | Physics | 12 | Active |
| US7328433B2 | Methods and apparatus for reducing memory latency in a software application | Physics | 11 | Expired |
| US7984431B2 | Method and apparatus for exploiting thread-level parallelism | Physics | 11 | Active |
| US7487502B2 | Programmable event driven yield mechanism which may activate other threads | Physics | 10 | Expired |
| US7882498B2 | Method, system, and program of a compiler to parallelize source code | Physics | 9 | Active |
| US9990206B2 | Mechanism for instruction set based thread execution of a plurality of instruction sequencers | Physics | 9 | Active |
| US8793675B2 | Loop parallelization based on loop splitting or index array | Physics | 9 | Active |
| US8205200B2 | Compiler-based scheduling optimization hints for user-level threads | Physics | 8 | Active |
| US7603546B2 | System, method and apparatus for dependency chain processing | Physics | 7 | Active |
| US9015688B2 | Vectorization of scalar functions including vectorization annotations and vectorized function signatures matching | Physics | 4 | Active |
| US7549146B2 | Apparatus, systems, and methods for execution-driven loop splitting and load-safe code hosting | Physics | 4 | Active |
| US8719819B2 | Mechanism for instruction set based thread execution on a plurality of instruction sequencers | Physics | 4 | Active |
| US11861761B2 | Graphics processing unit processing and caching improvements | Emerging Cross-Sectional Technologies | 3 | Active |
| US9009689B2 | Speculative compilation to generate advice messages | Physics | 3 | Active |
| US8607235B2 | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | Physics | 2 | Active |
| US8589901B2 | Speculative region-level loop optimizations | Physics | 2 | Active |
| US9910796B2 | Programmable event driven yield mechanism which may activate other threads | Physics | 1 | Active |
| US10877910B2 | Programmable event driven yield mechanism which may activate other threads | Physics | 1 | Active |
| US10459858B2 | Programmable event driven yield mechanism which may activate other threads | Physics | 1 | Active |
| US12147302B2 | Systems and methods for error detection and control for embedded memory and compute elements | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.