Selectable JTAG or trace access with data store and output
US7571364B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Dec 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3466
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are tra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.