Parallel parity checking for content addressable memory and ternary content addressable memory
US7571371B2 · kind B2 · utility
3Cited by
12References
31Claims
0Family size
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Key dates
| Filing date | Aug 18, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and arrangements for parallel parity checking for content addressable memory and ternary content addressable memory during compare cycles are disclosed. Further, methods and arrangements for remedying storage bit corruption are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.