Transient suppression semiconductor device
US7573080B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2008 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jun 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
The HBT-based transient suppression device contains a collector layer of a first conduction type, a base layer of a second conduction type, an emitter layer of the first conduction type, stacked in this order sequentially on a top side of a heavily doped substrate of the first conduction type. The doping concentration of the base layer is higher than that of the emitter and collector layers, and that the thickness of the collector layer is less than 300 nm, so that the BVCEO breakdown voltage is reduced below 5V Additionally, the thickness of the base layer is larger than the sum of the thickness of a section of the emitter-base depletion region extending into the base layer and the thickness of a section of the base-collector depletion region extending into the base layer, so that the base layer is not operated in a punch-through condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.