Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
US7573137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Sep 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20759
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal (142) bonds the spacers to the second chip, while the spacers space the first and second chips by a gap (105a) wide enough for placing the wire spans to the second set pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.