Dynamic data transfer control method and apparatus for shared SMP computer systems
US7574548B2 · kind B2 · utility
4Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 12, 2007 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.