Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components
US7574581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Aug 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination processing unit, receiving the command at the destination processing unit while the destination processing unit is processing program instructions, and accessing free-running, scan registers in clock-controlled components of the destination processing unit without interrupting processing of the program instructions by the destination processing unit. The access may be a read from status or mode registers of the destination processing unit, or write to control or mode registers. Many processing units can be interconnected in a ring topology, and the access command can be passed from the source processing unit through several other processing units before reaching the destination processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.