Circuit arrangement and method for secure data processing

US7574631B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Franz Klug · Munich, DE
• Steffen Sonnekalb · Munich, DE

Key dates

• Filing date: Feb 15, 2006
• Grant date: Aug 11, 2009
• Expiry date: Oct 26, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G07F7/1008
• WIPO field: Control
• WIPO sector: Instruments

Abstract

Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.