Method and apparatus for optimized parallel testing and access of electronic circuits
US7574637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2005 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jul 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i.e., simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local controllers over the communications path. The local controllers apply the stimulus data to the electronic circuits, receive resultant data generated by the circuits in response to the stimulus data, and locally verify the resultant data against the expected data substantially concurrently. When the communications path is implemented as an IEEE 1149.1 (JTAG) test bus, the primary controller can provide the expected and mask data to the local controllers over the TDO and TRSTN lines while the TAP controllers of the electronic circuits are in the Shift-IR or Shift-DR state to enable concurrent testing over a traditional five wire multi-drop IEEE 1149.1 test bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.