Fin structure and method of manufacturing fin transistor adopting the fin structure
US7575962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2007 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Oct 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
Provided are a fin structure and a method of manufacturing a fin transistor adopting the fin structure. A plurality of mesa structures including sidewalls are formed on the substrate. A semiconductor layer is formed on the mesa structures. A capping layer is formed on the semiconductor layer. Thus, the semiconductor layer is protected by the capping layer and includes a portion which is to be formed as a fin structure. A portion of an upper portion of the capping layer is removed by planarizing, and thus a portion of the semiconductor layer on upper surfaces of the mesa structures is removed. As a result, fin structures are formed on sides of the mesa structures to be isolated from one another. Therefore, a fin structure having a very narrow width can be formed, and a thickness and a location of the fin structure can be easily controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.