Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process
US7575977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2007 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.