Semiconductor chip package and multichip package
US7576431B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2004 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Feb 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a multichip package wherein a plurality of semiconductor chip packages (100) in each of which first electrode pads (16a) provided in a main surface of a semiconductor chip, and first bonding pads (20a) and first central bonding pads (18a) formed in an upper area of the main surface are respectively electrically connected by first redistribution wiring layers (24) in a one-to-one correspondence relationship, and second electrode pads (17b), and second bonding pads (22b) and second central bonding pads (18b) formed in an upper area of the main surface are respectively electrically connected by second redistribution wiring layers (26) in a one-to-one correspondence relationship, are stacked on one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.