Wafer-level solder bumps
US7576434B2 · kind B2 · utility
8Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2007 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Jun 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a semiconductor package having a support substrate coupled to a first semiconductor die, where the first semiconductor die includes first conductive bumps, and a second semiconductor die includes second conductive bumps, and where the first and second die are coupled by joints formed of the first and second conductive bumps and a solder material therebetween. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.