Patent · US Active

Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)

US7576668B2 · kind B2 · utility

1Cited by

13References

9Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Anand Hariraj Udupa · Richardson, US
Vikas Sinha · Austin, US
Nitin Agarwal · Bengaluru, IN
Visvesvararaya A. Pentakota · Savanuru, IN
Sandeep Kesrimal Oswal · Kanchinakote, IN

Key dates

Filing date	Nov 2, 2007
Grant date	Aug 18, 2009
Priority date	—
Expiry date	Nov 2, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/168
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.