Modified chip attach process
US7579213B2 · kind B2 · utility
2Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for assembling a package for a semiconductor device is described. The process includes reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.