Bonded-wafer superjunction semiconductor device
US7579667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2008 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Aug 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.