Reduced jitter amplification methods and apparatuses
US7579905B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Apr 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.