Discharge circuit for a word-erasable flash memory device
US7580289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2006 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Mar 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means and second switching means connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.