Memory with embedded error correction codes
US7581153B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 8, 2005 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.