Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses
US7582494B2 · kind B2 · utility
6Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Aug 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.