Recessed gate electrodes having covered layer interfaces and methods of forming the same
US7582931B2 · kind B2 · utility
2Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Jun 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.