ESD protection circuit
US7582937B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Jul 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
An ESD protection circuit includes a substrate, diode device, first snapback device, ring structure, second snapback device and a control circuit. The diode device is formed in the substrate. The first snapback device is formed in the substrate and includes a first heavy ion-doped region, a first gate and a second heavy ion-doped region. The first heavy ion-doped region is coupled to the diode device. The first gate is coupled to the second heavy ion-doped region. The ring structure is formed in the substrate and includes a third heavy ion-doped region located. The second gate is formed on the substrate between the second heavy ion-doped region and the third heavy ion-doped region to generate a second snapback device. The control circuit is connected to the third heavy ion-doped region for preventing the turn-on of a parasitic SCR formed in the substrate in a normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.