Vertically integrated system-in-a-package
US7582963B2 · kind B2 · utility
43Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Mar 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top surface of the first substrate, coupling one or more surface mount devices to a top surface of a second substrate, coupling the second substrate to a top surface of the first die, interconnecting the first substrate, the second substrate, and the first die, and encapsulating the first die, the second substrate and the surface mount devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.