Clock circuitry
US7583106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2007 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Jan 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.