System and method of counting leading zeros and counting leading ones in a digital signal processor
US7584233B2 · kind B2 · utility
3Cited by
8References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Oct 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.