Microprocessor comprising error detection means protected against an attack by error injection
US7584386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Oct 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. In one embodiment, the method comprises producing current cumulative signatures during the execution of a sequence, until a final cumulative signature is obtained, producing an error signal having a value active by default while the current cumulative signature is different to an expected signature, measuring a predetermined time interval that is substantially longer than the presumed duration of execution of the sequence, masking the error signal during the measurement of the time interval, and lifting the masking of the error signal when the time interval expires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.