Clock domain conflict analysis for timing graphs
US7584443B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Jul 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while preserving the original clock domain relationship of the edges in the path. To that end, the method includes generating a timing graph having a source instance, a destination instance and a plurality of edges defining a plurality of signal paths between the source instance and the destination instance. A plurality of clock domains is corresponded to the timing graph, with a subset of the plurality of edges being associated with more than one clock domain. From the subset, conflicting clock domains associated with a common edge are identified. In response to identification of the conflict, one of the clock domains is dissociated from one of the edges of the subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.