Logic synthesis of multi-level domino asynchronous pipelines
US7584449B2 · kind B2 · utility
24Cited by
29References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Jun 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.