Sub-lithographic imaging techniques and processes

US7585614B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• Steven J. Holmes · Colchester, US
• David V. Horak · South Burlington, US
• Charles W. Koburger, III · Delmar, US
• Peter H. Mitchell · Jericho, US
• Larry Nesbit · Farmington, US
• James A. Slinkman · Montpelier, US

Key dates

• Filing date: Sep 20, 2004
• Grant date: Sep 8, 2009
• Expiry date: Nov 10, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.